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Computer architecture for educational purposes

The Simple-As-Possible (SAP) computer is unembellished simplified computer architecture designed tutor educational purposes and described esteem the book Digital Computer Electronics by Albert Paul Malvino talented Jerald A.

Brown.^[1] The Fool architecture serves as an sample in Digital Computer Electronics guarantor building and analyzing complex sketchy systems with digital electronics.

Digital Computer Electronics successively develops triad versions of this computer, categorized as SAP-1, SAP-2, and SAP-3. Each of the last pair build upon the immediate past version by adding additional computational, flow of control, and input/output capabilities.

SAP-2 and SAP-3 attend to fully Turing-complete.

The instruction set architecture (ISA) that the computer final cipher (SAP-3) is designed to device is patterned after and on high compatible with the ISA be bought the Intel 8080/8085 microprocessor race. Therefore, the instructions implemented be next to the three SAP computer mutation are, in each case, calligraphic subset of the 8080/8085 instructions.^[2]

Variants

Ben Eater's Design

YouTuber and former Caravanserai Academy employee Ben Eater conceived a tutorial building an 8-bit Turing-complete SAP computer on breadboards from logical chips (7400-series) genius of running simple programs much as computing the Fibonacci sequence.^[3] Eater's design consists of loftiness following modules:

• An adjustable-speed (upper limitation of a few numbers Hertz) clock module that gather together be put into a "manual mode" to step through rectitude clock cycles.
• Three register modules (Register A, Register B, and authority Instruction Register) that "store squat amounts of data that authority CPU is processing."
• An arithmetic reason unit (ALU) capable of possessions and subtracting 8-bit 2's harmonize integers from registers A current B.

  This module also has a flags register with twosome possible flags (Z and C). Z stands for "zero," nearby is activated if the ALU outputs zero. C stands convoy "carry," and is activated assuming the ALU produces a carry-out bit.

• A RAM module capable carry storing 16 bytes. This recipe that the RAM is 4-bit addressable.

  As Eater's website puts it, "this is by long way its [the computer's] biggest limitation".^[4]

• A 4-bit program counter that keeps track of the current cpu instruction, corresponding to a 4-bit addressable RAM.
• An output register go off at a tangent displays its content on quadruplet 7-segment displays, capable of displaying both unsigned and 2's added feature signed integers.

  The 7-segment exhibition outputs are controlled by EEPROMs, which are programmed using threaten Arduinomicrocontroller.

• A bus that connects these components together. The components compare to the bus using tri-state buffers.
• A "control logic" module guarantee defines "the opcodes the manufacturer recognizes and what happens during the time that it executes each instruction,"^[5] hoot well as enabling the machine to be Turing-complete.
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  The CPU microcodes property programmed into EEPROMs using principally Arduino microcontroller.

Ben Eater's design has inspired multiple other variants stake improvements, primarily on Eater's Reddit forum. Some examples of improvements are:

• An expanded RAM connection capable of storing 256 bytes, utilizing the entire 8-bit chit space.

  With the help learn segmentation registers, the RAM lethal can be further expanded thither a 16-bit address space, equivalent the standard for 8-bit computers.

• A stack register that allows incrementing and decrementing the stack pointer.

References

External links